The present invention generally relates to the field of semiconductors, and more particularly relates to a method of fabricating FET semiconductor devices.
Self-aligning contacts (SAC) are typically used in semiconductor fabrication technology for CMOS (complementary metal-oxide-semiconductor) technology below 14 nm nodes, due to limited available space for placing transistor source/drain contacts. To place transistors as close as possible to each other, a source/drain contact of an FET transistor, for example, is merged with a source/drain contact of another adjacent FET transistor, thereby minimizing the distance between the two transistors on a substrate. However, the merged source/drain contact will be located very close to an adjacent gate of each of the two adjacent transistors. A thin spacer insulating material may be the only structure that separates the conductive source/drain contact and gate. This semiconductor structure, i.e., the source/drain contact and the gate separated by a thin insulating spacer creates a capacitor. This is an unintended capacitor with parasitic capacitance that increases power consumption and slows down the speed of a semiconductor circuit. The increased parasitic capacitance is undesirable for most circuit designs.